Title: Design and comparison of single and double edge synchronisation DLLs

Authors: Saman Mohammadi Mohaghegh; Reza Sabbaghi-Nadooshan

Addresses: Electrical Engineering Department, Islamic Azad University, Arak Branch, Arak, Iran ' Electrical Engineering Department, Islamic Azad University, Central Tehran Branch, Niayesh Building, Emamhasan Blvd., Pounak, Tehran, Iran

Abstract: The main point of this paper is to compare single edge with double edge synchronisation DLL. In order to reduce challenges of designing double edge DLL, in this paper, proper blocks with suitable characteristic for each MOSFET were used. Both single and double edge circuits are designed and simulated using 0.18 µm CMOS technology with 1.8 v supply voltage. The operation frequency range in both circuits is from 750 MHz to 1 GHz. The locking time of single edge and double edge synchronisation DLL is less than 15 ns and 20 ns within the operating frequency band, respectively. The maximum power consumption of single and double edge DLL circuit at 1 GHz is 2.35 and 3.4 mW, respectively. The RMS jitter for single and double edge synchronisation DLL at 1 GHz is 0.908 and 0.771 ps and the peak-to-peak jitter at 1 GHz is 9.9 and 18.13 ps, respectively. Duty-cycle error for single edge DLL is 50 ± 0.6% while for double edge DLL is 50 ± 0.90%. RMS jitter, peak-to-peak jitter, power consumption and also duty cycle error are calculated by HSPICE simulator.

Keywords: delay-locked loops; jitter; multistage clock buffer; MCB; voltage controlled delay line; single edge synchronisation DLLs; double edge synchronisation DLLs; MOSFETs; circuit design; circuit simulation; locking time; power consumption; duty cycle error.

DOI: 10.1504/IJCAD.2015.072608

International Journal of Circuits and Architecture Design, 2015 Vol.1 No.4, pp.295 - 308

Received: 21 Jun 2014
Accepted: 21 Dec 2014

Published online: 22 Oct 2015 *

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