Authors: Georgios Dimitriou; Athanasios Tziouvaras
Addresses: Department of Electrical and Computer Engineering, University of Thessaly, 37 Glavani & 28th October Str, 38221 Volos, Greece ' Department of Electrical and Computer Engineering, University of Thessaly, 37 Glavani & 28th October Str, 38221 Volos, Greece
Abstract: Computer architects have focused on advanced processor designs that achieve high performance through multiple cores and multiple threads, and at the same time keep power dissipation low. In this work, we propose a processor back end, specifically designed for rapid loop execution and low power dissipation. This back end consists of a network of functional unit nodes, in which instructions of the loop body are issued only once until loop completion. In this way, we exploit both instruction-level and data-flow parallelism. We attempt to decrease power consumption by turning off the front end and all unused functional units. Simulation results show that the proposed back end can accelerate Livermore loops by up to N/k, for a network of N units and loop body size of N instructions, and an issue rate of k instructions per cycle, when compared to scalar or superscalar RISC execution.
Keywords: processor architecture; processor back end; functional units; rapid loop execution; loop acceleration; dataflow parallelism; on-chip interconnects; low power dissipation; loop distribution; power consumption; simulation.
International Journal of Innovation and Regional Development, 2015 Vol.6 No.3, pp.267 - 284
Available online: 12 Aug 2015 *Full-text access for editors Access for subscribers Purchase this article Comment on this article