Title: Multiple logic styles for low power 4:1 multiplexer in 45 nm technology

Authors: Meenakshi Mishra; Shyam Akashe

Addresses: Institute of Technology & Management, Gwalior, Madhya Pradesh, India ' Institute of Technology & Management, Gwalior, Madhya Pradesh, India

Abstract: Complementary Metal Oxide Semiconductor (CMOS) memory elements and data control structures consists of multiplexer as the basic components. The low-power consumption is one of the most important concerns of the system design. Different styles for low power designs in high speed applications have been developed. In this paper, the multiple logic styles are used to design a low power 4:1 Multiplexer (MUX). The leakage current, power consumption, delay and transistor count are compared for different logic styles of 4:1 MUX. The transmission gate multiplexer consumes low power compared with respect to other logic styles. Static MUX consists of the more transistors in compare to the NMOS MUX. The outcome represents that NMOS pass transistor logic multiplexer performs the task with minimal delay and minimum power consumption with fewer numbers of transistors. The designed circuit is realised in 45 nm technology, from a 0.7 V supply voltage under 27°C.

Keywords: transmission gate multiplexers; low power consumption; leakage current; static CMOS; pass transistor logic; LEAP; pseudo NMOS; multiple logic styles; multiplexer design.

DOI: 10.1504/IJSISE.2015.070487

International Journal of Signal and Imaging Systems Engineering, 2015 Vol.8 No.3, pp.166 - 176

Received: 22 Aug 2012
Accepted: 28 Jan 2013
Published online: 08 Jul 2015 *

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