Title: New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources

Authors: Shirin Rezaie; Reza Faghih Mirzaee; Keivan Navi; Omid Hashemipour

Addresses: Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran 1477893855, Iran ' Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran 37541-374, Iran ' Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran 1983963113, Iran ' Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran 1983963113, Iran

Abstract: Ternary minimum (AND) and maximum (OR) functions are implemented in this paper based on dynamic logic style, where the clock signal evaluates combinational circuits periodically. Unlike previously presented designs, additional voltage sources are not required in the proposed structures. Transistors divide voltage to achieve standard ternary functions. An initial design is modified gradually to reach a high-performance design with reduced transistor-count and decreased switching activity. New circuits are simulated with carbon nanotube field effect transistor technology in different situations. Simulation results show that the proposed cells are suitable for low-power and high-frequency applications.

Keywords: dynamic ternary logic; ternary AND; ternary OR; low power; CNFET; ternary minimum; ternary maximum; carbon nanotubes; CNTs; FETs; field effect transistors; simulation; nanotechnology.

DOI: 10.1504/IJHPSA.2015.070387

International Journal of High Performance Systems Architecture, 2015 Vol.5 No.3, pp.153 - 165

Received: 01 Jul 2014
Accepted: 25 Oct 2014
Published online: 04 Jul 2015 *

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