Title: Pipelined hardware design of self tuning controller with on-chip parameter estimator

Authors: S.P. Joy Vasantha Rani

Addresses: Department of Electronics Engineering, Madras Institute of Technology Campus, Anna University, Chennai – 600 044, India

Abstract: This paper intends to propose a pipelined design of floating point-based self tuning controller (STC) with on-chip process parameter estimator using recursive least square (RLS) algorithm used for real time control applications. The parameter estimation algorithm runs continuously to allow the model of the system to be updated at each sample interval as changes occur in the process and the algorithm estimates the unknown process parameters recursively based on the minimisation of the least squares error. The estimated parameters are validated with actual parameters of first and second discrete single input single output (SISO) linear processes. The proposed pipelined design of STC is analysed with the second order process. The process is controlled by RST controller and its parameters are identified with minimum degree pole placement technique. The design is implemented in very high-speed integrated circuit hardware description language (VHDL) and is tested using Virtex IV device 4VLX200ff1513. The maximum operating frequency of pipelined design of STC is 146.735 MHz.

Keywords: self tuning control; field programmable gate arrays; FPGA; recursive least squares; RLS; on-chip parameter estimator; RST controller; minimum degree pole placement; floating point arithmetic; single precision; VHDL; pipelined hardware design; controller design; parameter estimation.

DOI: 10.1504/IJHPSA.2015.070384

International Journal of High Performance Systems Architecture, 2015 Vol.5 No.3, pp.127 - 140

Available online: 04 Jul 2015 *

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