Title: Dynamic partially reconfigurable architecture for fast Fourier transform computation

Authors: Hung-Lin Chao; Cheng-Chien Wu; Chun-Yang Peng; Chun-Hsien Lu; Jih-Sheng Shen; Pao-Ann Hsiung

Addresses: Department of Computer Science and Information Engineering, National Chung Cheng University, 168, University Road, Min-Hsiung, Chiayi, 62102, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, 168, University Road, Min-Hsiung, Chiayi, 62102, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, 168, University Road, Min-Hsiung, Chiayi, 62102, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, 168, University Road, Min-Hsiung, Chiayi, 62102, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, 168, University Road, Min-Hsiung, Chiayi, 62102, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, 168, University Road, Min-Hsiung, Chiayi, 62102, Taiwan

Abstract: Fast Fourier transform (FFT) is one of the most frequently used computation kernels in modern digital systems, such as in image and signal processing applications. Derivative FFT designs have been proposed for different purposes for a single application. In this work, we propose a novel scalable FFT architecture called dynamic partially reconfigurable fast Fourier transform (DPRFFT) that can support multi-standard applications simultaneously. DPRFFT has multiple pipelines that are time-multiplexed among multiple applications such that significant savings in hardware resources is achieved, under very insignificant performance overhead. DPRFFT performs variable-length FFT from 64 to 8192 points, which cover most of the frequently used modern computing standards.

Keywords: fast Fourier transform; FFT; time-division multiplexing; TDM; dynamic partial reconfiguration; hybrid memory-pipeline reconfigurable architecture; MIMO; computing standards.

DOI: 10.1504/IJES.2014.063818

International Journal of Embedded Systems, 2014 Vol.6 No.2/3, pp.207 - 215

Available online: 22 Jul 2014 *

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