Authors: Rongjie Yan; Min Yu; Kai Huang; Xiaomeng Zhang
Addresses: State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences, Beijing, 100190, China ' Institute of VLSI Design, Zhejiang University, Hangzhou, 310013, China ' Institute of VLSI Design, Zhejiang University, Hangzhou, 310013, China ' Institute of VLSI Design, Zhejiang University, Hangzhou, 310013, China
Abstract: Increasing complexity of embedded systems brings a big challenge for designers to satisfy requirements for both high-performance and programmability. Automatic multi-threaded code generation facilitates MPSoC-based programming greatly. Apart from the savings on programming effort, system performance is also an important issue to be considered during code generation process. As thread communication is quite frequent in multi-threaded code, system performance will be improved by reducing communication cost. Communication pipeline technique applies distributed memory server for parallel execution between message passing and functional tasks, to reduce the cost caused by communication between different processors. The technique can be applied directly to communicating threads in acyclic topologies. To maximise its application, we also provide a solution to apply the technique to cyclic topologies with allocable delay units. Furthermore, we introduce a scheduling strategy for local threads to improve communication efficiency and processor usage. Experimental results demonstrate the performance improvements with the proposed techniques.
Keywords: multi-threaded code generation; communication pipeline; cyclic topology; scheduling strategy; embedded systems; thread communication.
International Journal of Embedded Systems, 2014 Vol.6 No.2/3, pp.124 - 134
Available online: 22 Jul 2014 *Full-text access for editors Access for subscribers Purchase this article Comment on this article