Authors: Jian Li, Hu-Jun Wang, Hui-Zhong Wu
Addresses: SiWei Computer Corporation, ZhuJiang Road 448, NanJing 210018, P.R. China. ' Department of Computer Science, NanJing University of Science and Technology NanJing 210094, P.R. China. ' Department of Computer Science, NanJing University of Science and Technology NanJing 210094, P.R. China
Abstract: The interconnection network (IN) is one of the major factors which determine the performance of a multiprocessor system. It is imperative to have a model by which the efficiency of the IN can be correctly evaluated. This paper presents an m-level HMPMB multiprocessor system and analyses its bandwidth performance. Two models are developed for the hierarchically equally likely case and favourite case, respectively. They show that the m-level HMPMB multiprocessor system performs well and is fairly close to a typical memory-oriented partial multiple bus system (MPMB) for high rates of favourite requests.
Keywords: multiprocessors; bandwidth; hierarchical systems; performance analysis; interconnection networks; bus system.
International Journal of Computer Applications in Technology, 1996 Vol.9 No.4, pp.174 - 180
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