Authors: Hameedah Sultan; Gayathri Ananthanarayanan; Smruti R. Sarangi
Addresses: Department of Electrical Engineering, Indian Institute of Technology, New Delhi – 110 106, India ' School of Information Technology, Indian Institute of Technology, New Delhi – 110 016, India ' Computer Science and Engineering, Indian Institute of Technology, New Delhi – 110 016, India
Abstract: Since the end of the nineties, power dissipation has been regarded as a first order design constraint in processors. Increased power dissipation along with the resultant rise in die temperature is considered as the single largest bottleneck for increasing processor frequency and complexity. Consequently, it is very important from both a technical as well as commercial perspective to accurately estimate processor power such that designers can tailor their architecture, software and systems to minimise power consumption. In this paper, we provide a survey of most of the processor specific power estimation techniques proposed after the mid nineties. Specifically, we look at estimating power both at design time as well as runtime. The former approach is more suitable for early stage architectural exploration, and the latter approach is more germane to creating power efficient application software. We broadly focus on estimating power using system level models, architectural simulation, hardware performance counters, on-chip temperature profiles, and program execution profiles. We showcase a broad range of methods for power estimation using simulators, compilers, profilers, and sophisticated mathematical analysis routines.
Keywords: processor power estimation; performance counters; architectural tools; SystemC; power dissipation; architectural simulation; hardware performance counters; on-chip temperature profiles; program execution profiles.
International Journal of High Performance Systems Architecture, 2014 Vol.5 No.2, pp.93 - 114
Received: 10 Dec 2013
Accepted: 11 Dec 2013
Published online: 26 May 2014 *