Title: Characteristics of gate-all-around polycrystalline silicon channel SONOS flash memory

Authors: Joo Yun Seo; Sang-Ho Lee; Se Hwan Park; Wandong Kim; Do-Bin Kim; Byung-Gook Park

Addresses: Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea ' Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea ' Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea ' Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea ' Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea ' Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

Abstract: In this study, the gate-all-around (GAA) poly-Si channel flash memories with a nitride charge trap layer (Si3N4) have been successfully fabricated. Electrical characteristics of fabricated devices including the threshold voltage shift with program/erase operation have been investigated. Gate structures were formed differently according to each defined channel width. Results show that devices with the gate-all-around structure have superior program efficiency. To investigate the effect of gate structure on the program efficiency, TCAD simulation was carried out. Another issue of the fabricated devices is poor erase operation due to the quality of the blocking oxide. This issue has been studied through the capacitor composed of the same stack structure, and the way to improve the erase operation has been proposed.

Keywords: SONOS flash memory; GAA; gate-all-around; nanowires; charge trapping flash memory; nanoelectronics; nanotechnology; silicon nitride; Si3N4; gate structures; TCAD simulation; polycrystalline silicon channel.

DOI: 10.1504/IJNT.2014.059815

International Journal of Nanotechnology, 2014 Vol.11 No.1/2/3/4, pp.116 - 125

Available online: 13 Mar 2014 *

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