Title: Low power high throughput reconfigurable stream cipher hardware VLSI architectures

Authors: R. Sakthivel; M. Vanitha; Harish M. Kittur

Addresses: School of Electronics Engineering (SENSE), VIT University, Vellore, Tamilnadu-632014, India ' School of Information Technology, VIT University, Vellore, Tamilnadu-632014, India ' School of Electronics Engineering (SENSE), VIT University, Vellore, Tamilnadu-632014, India

Abstract: This work reports power efficient high throughput VLSI hardware architecture for RC4 stream cipher. Two VLSI architectures have been developed for RC4 algorithm which shows power efficiency and frequency/throughput improvement compared to the existing FPGA implementations. Naturally, the ASIC implementation of the same shows more power and PDP reduction compared with existing FPGA architectures. The first architecture Proposed-I (S-box) developed by replacing the RAM based S-box, with combinational circuits providing a means for reducing the critical path. Pipelining applied in the S-box increases the speed and reduces the power consumed. Second architecture Proposed-II (LFSR) has been developed using LFSR and FSM based control for key scheduling algorithm. These architectures were first implemented by targeting for FPGA and the same designs were targeted for an ASIC chip. Finally, a novel VLSI architecture has been proposed with an intention of sharing the S-box resources for RC4 and AES algorithm expectedly saving area and power.

Keywords: power efficiency; combinational logic S-box; key scheduling algorithm; KSA; pipelining; RC4 stream cipher; AES; low power VLSI architectures; high throughput VLSI architectures; reconfigurable hardware; symmetric key cryptography; computer security.

DOI: 10.1504/IJICS.2014.059785

International Journal of Information and Computer Security, 2014 Vol.6 No.1, pp.1 - 11

Received: 29 Nov 2012
Accepted: 13 Jul 2013
Published online: 02 Jul 2014 *

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