Title: Systolic traffic modelling in network on chip

Authors: Ming-Wei Qin; Jian-Hao Hu; Shang Ma

Addresses: National Key Laboratory of Science and Technology on Communications, University of Electronic Science and Technology of China, Chengdu 611731, China; School of Information Engineering, Southwest University of Science and Technology, Mianyang 621010, China ' National Key Laboratory of Science and Technology on Communications, University of Electronic Science and Technology of China, Chengdu 611731, China ' National Key Laboratory of Science and Technology on Communications, University of Electronic Science and Technology of China, Chengdu 611731, China

Abstract: In this paper, we present the systolic architecture unit in NoC and address the fundamental issue of traffic modelling for systolic architectures unit in SoC design. We improve the synthetic trace generation method in order to simulate in systolic architectures unit and analyse the effect of the systolic architecture for traffic model, give the function H_Y=F(H_X1,H_X2) by simulating and surface fitting for 2-input and 1-output systolic architecture unit traffic model. Our proposed technique allows designers implementing on-chip communication networks to model the traffic of any application by systolic architectures unit more effectively. This will enable systems designers to optimally their mapping and routing, architectures, and so on. Ultimately, designers will achieve optimal trade-off performance metrics and application quality.

Keywords: network on chip; NoC; systolic architecture unit; traffic modelling; Hurst exponent; on-chip communication networks; simulation; surface fitting.

DOI: 10.1504/IJWMC.2014.059715

International Journal of Wireless and Mobile Computing, 2014 Vol.7 No.2, pp.187 - 193

Received: 02 Jul 2013
Accepted: 21 Jul 2013
Published online: 31 Oct 2014 *

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