Title: Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link

Authors: M. Maheswari; G. Seetharaman

Addresses: Department of Electronics and Communication Engineering, J.J. College of Engineering and Technology, Tiruchirappalli, Tamil Nadu, 620009, India ' Oxford Engineering College, Tiruchirappalli, Tamil Nadu, 620009, India

Abstract: With the shrinking geometry, interconnection wires in network-on-chip (NoC) will be exposed to different noise sources such as crosstalk coupling and supply voltage fluctuation that cause random and burst errors. These errors affect the reliability of NoC. Hence error control codes are incorporated to make the NoC robust against errors. In this paper, we propose a novel low complex error control code to correct random and burst errors and simultaneously avoid crosstalk. The proposed error control code uses a novel triplicate add parity (TAP) scheme to avoid crosstalk in the interconnection links. The proposed error control code can detect burst errors of three and correct random or burst errors up to two. Hybrid automatic repeat request (HARQ) system is employed when burst errors of three occurs. The proposed error control code outperforms the existing error control code in terms of residual flit error rate and energy consumption.

Keywords: error correction code; HARQ; hybrid automatic repeat request; NoC; network-on-chip; on-chip-interconnect; TAP; triplicate add parity; crosstalk avoidance; residual flit error rate; energy consumption.

DOI: 10.1504/IJCAT.2014.059097

International Journal of Computer Applications in Technology, 2014 Vol.49 No.1, pp.80 - 88

Received: 08 May 2021
Accepted: 12 May 2021

Published online: 03 Feb 2014 *

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