Authors: Bouraoui Ouni; Abdellatif Mtibaa
Addresses: Laboratory of Electronic and Microelectronic, Faculty of Sciences, University of Monastir, Monastir 5000, Tunisia ' Laboratory of Electronic and Microelectronic, Faculty of Sciences, University of Monastir, Monastir 5000, Tunisia
Abstract: In this paper, we present the famous temporal partitioning algorithms that temporally partition a data flow graph on reconfigurable systems. We have classified these algorithms into four classes: 1) whole latency optimisation algorithms; 2) whole communication cost optimisation algorithms; 3) whole area optimisation algorithms; 4) whole latency-communication cost optimisation algorithms. These algorithms can be used to solve the temporal partitioning problem at the behaviour level.
Keywords: temporal partitioning; reconfigurable architectures; FPGA engineering; field programmable gate arrays; VLSI applications; computer aided design; CAD; data flow graphs; latency optimisation; communication cost optimisation; area optimisation.
International Journal of Computational Science and Engineering, 2014 Vol.9 No.1/2, pp.21 - 33
Available online: 15 Jan 2014 *Full-text access for editors Access for subscribers Purchase this article Comment on this article