Title: A survey on B*-Tree-based evolutionary algorithms for VLSI floorplanning optimisation

Authors: D. Gracia Nirmala Rani; S. Rajaram

Addresses: Department of Electronics and Communication, Thiagarajar College of Engineering, Madurai 625015, Tamilnadu, India ' Department of Electronics and Communication, Thiagarajar College of Engineering, Madurai 625015, Tamilnadu, India

Abstract: In the unpredictable recent developments in the application of VLSI technology, CAD tools are important for bringing high system performance. The VLSI floorplanning problem aims to arrange a set of modules on a rectangular chip area so as to optimise an appropriate measure of performance. There are two factors in general when dealing with the floorplanning problem. The first one is to find an appropriate topological representation in the form of a data structure. The second aspect considers the application of a stochastic search method on the representation to find an optimised floorplan. Current VLSI floorplanners must include multiple metrics in their objective function such as area, wire length and temperature parameters. Hence an optimisation engine is necessary for the floorplanning problem that can handle multiple metrics. In this paper, we present a review/tutorial of the optimisation techniques based on B*-Tree representation in VLSI floorplanning that have been recently proposed.

Keywords: CAD VLSI; VLSI floorplanning; B*-Tree; simulated annealing; hybrid evolutionary algorithms; hybrid genetic algorithms; differential evolutionary algorithms; optimisation.

DOI: 10.1504/IJCAT.2013.058350

International Journal of Computer Applications in Technology, 2013 Vol.48 No.4, pp.281 - 287

Received: 08 May 2021
Accepted: 12 May 2021

Published online: 18 Dec 2013 *

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