Article: A programmable multi-step cyclic Vernier time-to-digital converter Journal: International Journal of Circuits and Architecture Design (IJCAD) 2013 Vol.1 No.1 pp.41 - 61 Abstract: A new architecture for a time-to-digital converter (TDC) is presented in this paper. The programmability feature of the new proposed architecture allows for the reusability of the design for various applications requiring different resolution, throughput, area and power constraints. One of the main motives behind this work (besides the programmability feature) is trying to resolve the inherent TDC design tradeoffs between resolution, throughput and complexity. The new TDC was implemented using the TSMC 65 nm technology. A detailed transistor level design along with the system level analysis is presented. For a reliable operation, a new auto calibration scheme is proposed that guarantees the successful operation of the system. Simulation results show the successful operation of the proposed TDC and its ability to auto calibrate itself for any process corner. As an example, for a resolution of 4 ps with an input range of 1 ns, the proposed TDC had a throughput of 45 MS/s while maintaining a DNL of 0.85 LSB and INL of 0.93 LSB. Inderscience Publishers - linking academia, business and industry through research

You can view the full text of this article for free using the link below.

Title: A programmable multi-step cyclic Vernier time-to-digital converter

Authors: Mina Raymond; Maged Ghoneima; Yehea Ismail

Addresses: Power Management Research Lab, Iowa State University, 2117 Coover Hall, Ames, IA 50011, USA ' Center of Nanoelectronics and Devices (CND), Zewail City of Science and Technology, 90th St, 5th Settlement, New Cairo, Cairo, Egypt; American University in Cairo, 90th St, 5th Settlement, New Cairo, Cairo, Egypt ' Center of Nanoelectronics and Devices (CND), Zewail City of Science and Technology, 90th St, 5th Settlement, New Cairo, Cairo, Egypt; American University in Cairo, 90th St, 5th Settlement, New Cairo, Cairo, Egypt

Abstract: A new architecture for a time-to-digital converter (TDC) is presented in this paper. The programmability feature of the new proposed architecture allows for the reusability of the design for various applications requiring different resolution, throughput, area and power constraints. One of the main motives behind this work (besides the programmability feature) is trying to resolve the inherent TDC design tradeoffs between resolution, throughput and complexity. The new TDC was implemented using the TSMC 65 nm technology. A detailed transistor level design along with the system level analysis is presented. For a reliable operation, a new auto calibration scheme is proposed that guarantees the successful operation of the system. Simulation results show the successful operation of the proposed TDC and its ability to auto calibrate itself for any process corner. As an example, for a resolution of 4 ps with an input range of 1 ns, the proposed TDC had a throughput of 45 MS/s while maintaining a DNL of 0.85 LSB and INL of 0.93 LSB.

Keywords: time measurement; time-to-digital converters; TDC; data conversion; calibration systems; architecture design; design reuse; programmability; simulation.

DOI: 10.1504/IJCAD.2013.057454

International Journal of Circuits and Architecture Design, 2013 Vol.1 No.1, pp.41 - 61

Received: 02 Mar 2013
Accepted: 05 Apr 2013
Published online: 05 Jul 2014 *

Full-text access for editors Full-text access for subscribers Free access Comment on this article

Title: A programmable multi-step cyclic Vernier time-to-digital converter

Keep up-to-date