Authors: Ashok Kumar Suhag; Satdev Ahlawat; Vivek Shrivastava; Nidhi Singh
Addresses: Gautam Buddha University, Greater Noida, 201312, India ' Indian Institute of Science, Bangalore, 560012, India ' National Institute of Technology, Delhi, 110077, India ' Gautam Buddha University, Greater Noida, 201312, India
Abstract: Excessive switching activity in test mode results in higher power dissipation than normal mode of operation and becoming a serious issue, in order to avoid reliability problems. Scanning of test vectors in test mode causes unnecessary switching in combinational block which can be reduced by gating methods. Gating the outputs of scan cells is a recently proposed very efficient low power test technique, which reduces the scan shift power significantly. However, the output gating techniques impacts the performance severely. In this paper, we propose a modified transistor level design of a scan flip-flop for critical paths, which eliminates the unnecessary switching in combinational circuit during shift phase of a scan-based test, without the impact on performance as in earlier scan flip-flop output gating schemes (Khatri and Ganeshan, 2008). The new scan flop design not only eliminates the performance overhead of output gating but also improves the performance of the scan flop by 32.84% (Khatri and Ganeshan, 2008) and 11.5% (Yang et al., 2008). The new flip-flop disables the output and uses an alternate path for shifting the test vectors. This approach have area overhead of six extra transistors but improves the overall performance of scan flip-flop, so this approach is better suited for critical paths. This also allows us to increase the shift frequency in designs where shift power dissipation puts upper bound on the frequency, and hence reduces test application time.
Keywords: scan-based testing; scan flip-flop; low power testing; launch on capture; launch on shift; timing critical paths; output gating; performance overheads; excessive switching; power dissipation; shift frequency.
International Journal of Circuits and Architecture Design, 2013 Vol.1 No.1, pp.62 - 73
Received: 28 Dec 2012
Accepted: 05 Apr 2013
Published online: 29 Oct 2013 *