Authors: Mohamed Trabelsi; Lazhar Ben-Brahim; Tomoki Yokoyama; Atsuo Kawamura
Addresses: Electrical Department, College of Engineering, Qatar University, P.O. Box 2713, Doha, Qatar ' Electrical Department, College of Engineering, Qatar University, P.O. Box 2713, Doha, Qatar ' Department of Robot and Mechatronics, School of Science and Technology for Future Life, Tokyo Denki University, 5 Senju-Asahimachi, Adachi-ku, Tokyo, Japan ' Faculty of Engineering, Intelligent Systems Engineering, Department of Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Japan
Abstract: The fast rise time of output voltage pulses (dv/dt) in PWM multi-level inverters (MLI) is one of the major factors of the increase of electromagnetic interference EMI and the shortness of motor useful life. Moreover, irregular voltage pulses, which only appear for critical modulation indexes, can deepen this interference phenomenon. To overcome this problem, this paper proposes an adaptive hysteresis dead-band (AHDB)-based space vector PWM (SVPWM) method for MLI. The proposed scheme is developed for multilevel cascaded H-bridge (CHB) inverters. In the proposed strategy, general dwell-time equations were derived to achieve the SVPWM for any n-level inverter. Moreover, the dwell-times calculation was made easy by using only two parameters defining regions for a given sector. Furthermore, to remove all irregular pulses from the output voltage, the dead-band of the hysteresis was made variable. Both theoretical analyses and simulation results are presented to show the effectiveness of the proposed method.
Keywords: space vector PWM; SVPWM; pulse width modulation; dynamic dwell-times; irregular voltage pulses compensation; adaptive hysteresis dead-band; AHDB; multi-level inverters; power electronics; electromagnetic interference; EMI; simulation.
International Journal of Power Electronics, 2013 Vol.5 No.3/4, pp.280 - 300
Received: 02 Mar 2013
Accepted: 08 Jul 2013
Published online: 06 Oct 2013 *