Authors: Yanhua Liu; Ying Ruan; Zongsheng Lai
Addresses: Institute of Microelectronics Circuit and System East China Normal University, Shanghai 200062, China; Jiangsu Provincial Key Lab of ASIC Design Nantong University, Nantong 226000, China ' Institute of Microelectronics Circuit and System East China Normal University, Shanghai 200062, China ' Institute of Microelectronics Circuit and System East China Normal University, Shanghai 200062, China
Abstract: Three Dimensional Network on Chip (3D NoC), which reduces the average number of hops traversed by a packet, can achieve better performance than the traditional 2D NoC. However, when routers deliver packets in 3D NoC, more energy consumption is needed. High-energy consumption and small packaging density will cause excessive heat, which increases vulnerability of the system in performance and reliability. In this paper, we present a low-energy consumption mapping algorithm based on the symmetry of the architecture and construct a deadlock-free routing algorithm using mapping result information. Our proposed algorithms can reduce the total energy consumption of communication and achieve a good system performance under the bandwidth constraints. To evaluate the efficacy of the algorithms, we perform experiments on several benchmarks and compare the proposed algorithms with other existing algorithms. Experimental results show that, for complex benchmarks, our proposed algorithms get better results than others.
Keywords: 3D NoC; 3D network on chip; low energy consumption; energy consumption mapping; deadlock-free routing.
International Journal of Computer Applications in Technology, 2013 Vol.47 No.1, pp.1 - 13
Published online: 03 Jun 2013 *Full-text access for editors Access for subscribers Purchase this article Comment on this article