Authors: Yi Wang; Hailong Shi; Li Cui
Addresses: Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China ' Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China ' Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
Abstract: The practical applications of Wireless Sensor Networks (WSNs) in vulnerable areas require the communication data possessing confidentiality, integrity and freshness. In this paper, we present the implementation and simulation of a hardware security coprocessor called EasiSec based on system-on-chip (SoC) technology for WSN. Compared with existing works, our unique features include: (1) A fingerprint-based key management (FKM) module to extract key elements from program memory and build secret keys for cryptographic coprocessor, which can resist the key compromise impersonation attack; (2) A reusable optimised logic cell (ROLC) to complete encryption and decryption, and minimise the hardware overhead; (3) An authentication module based on Linear Feedback Shift Register (LFSR) to provide two-party data with integrity and freshness. The design is mapped on FPGA and ASIC design. Results show the hardware overhead of our design is 16.5% less than common designs and the execution time is shorter than other coprocessors.
Keywords: system-on-a-chip; SoC; fingerprint based key management; hardware security coprocessors; wireless sensor networks; WSNs; reusable logic cells; optimised logic cells; secret keys; cryptography; encryption; decryption; hardware overhead; authentication; linear feedback shift register; LFSR; FPGA design; ASIC design.
International Journal of Sensor Networks, 2013 Vol.13 No.2, pp.85 - 93
Published online: 05 May 2013 *Full-text access for editors Access for subscribers Purchase this article Comment on this article