Title: Investigation of the kink effect in indium-doped silicon for sub 100 nm N channel MOSFET technology

Authors: Abdelaali Fargi; Neila Hizem; Adel Kalboussi

Addresses: Laboratoire de Microélectronique et Instrumentation, Departement de Physique, Faculté des Sciences de Monastir, Avenue de l'Environnement, Monastir 5000, Tunisia ' Laboratoire de Microélectronique et Instrumentation, Departement de Physique, Faculté des Sciences de Monastir, Avenue de l'Environnement, Monastir 5000, Tunisia ' Laboratoire de Microélectronique et Instrumentation, Departement de Physique, Faculté des Sciences de Monastir, Avenue de l'Environnement, Monastir 5000, Tunisia

Abstract: The increasing interest in nanoelectronic devices that require cryogenic temperatures to function has led to an increased need for analog CMOS circuits. Using indium, an acceptor dopant in silicon, a heavy atom with a low diffusion coefficient is potentially suitable for doping the channel of CMOS transistors. These transistors when operated at low temperatures at which the majority of carriers experience freeze-out exhibit an effect known as the kink effect. In this paper, we will discuss the kink effect presented in the drain current-voltage measurement curves at low temperature. The variation of conductance and transconductance was calculated from measurements of the drain current versus gate and drain voltages. Capacitance-voltage versus temperature was measured to investigate the freeze-out of carriers that could be related to indium in the p-type doping region and then Deep Level Transient Spectroscopy (DLTS) measurement was carried out to determine the trap level and its activation energy. The effect of traps related to indium in Si NMOS transistors is investigated with the DLTS technique and the existence of a relationship between the kink effect and the active indium trap level situated at 0.18 eV from valence band is also discussed.

Keywords: silicon MOSFET; I-V characteristics; DLTS; impact ionisation; kink effect; retrograde doping profile; indium trap level; nanotechnology; nanoelectronics; cryogenic temperatures; CMOS transistors; low temperature.

DOI: 10.1504/IJNT.2013.053521

International Journal of Nanotechnology, 2013 Vol.10 No.5/6/7, pp.523 - 532

Received: 08 May 2021
Accepted: 12 May 2021

Published online: 26 Apr 2013 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article