Authors: Ievgen Korotkyi; Oleksandr Lysenko
Addresses: Department of Design of Electronic Digital Equipment (DEDEC), National Technical University of Ukraine 'Kyiv Polytechnic Institute', Polytechnic 16 Street, 03056 Kyiv, Ukraine ' Department of Design of Electronic Digital Equipment (DEDEC), National Technical University of Ukraine 'Kyiv Polytechnic Institute', Polytechnic 16 Street, 03056 Kyiv, Ukraine
Abstract: A new method of link aggregation (LAG) in networks-on-chip (NoC) is investigated. This method considerably (by 152 ÷ 300%) increases a network saturation threshold by connection of topologically adjacent routers using of multiple physical links. The authors consider several ways how to improve simulation performance of digital circuits. An algorithm, which illustrates operation of high-performance SystemC model of a NoC router with LAG, is proposed. This paper also includes results of computer simulation of the suggested fast SystemC model and its synthesisable System Verilog counterpart. The results of ModelSim simulation show that usage of proposed SystemC model instead of its System Verilog analogue reduces the duration of simulation in ten times and diminish the required memory in 121 times. Herewith, the prediction error for saturation threshold of NoC does not exceed 6.1%.
Keywords: network on chip; NoC; link aggregation; routing; FPGA; field programmable gate arrays; simulation; SystemC; network saturation threshold.
International Journal of Embedded Systems, 2013 Vol.5 No.1/2, pp.3 - 12
Received: 21 Feb 2012
Accepted: 11 Sep 2012
Published online: 15 Feb 2013 *