Authors: Amit Zinzuwadiya; Renu Verma
Addresses: Amdocs, Gurgaon, Haryana, 122001, India ' Rama Institute of Technology, Kanpur, 208009, India
Abstract: In this paper, as technology scales higher, reliability of network on chip (NoC) becomes key issue. It decreases the transistor reliability by connecting the increasing number of on-chip resources. Consequently, this paper presents an efficient fault tolerant routing algorithm for the NoC architecture. We propose acyclic LBDRe which is based on extended logic-based distributed routing (LBDRe) array. Minimal set of turns are prohibited to avoid deadlock. The algorithm guarantees that not more than 1/3 of all turns in the NoC architecture become prohibited. The proposed routing algorithm outperforms substantially the existing fault tolerant routing algorithms. Simulation results show that the proposed method can noticeably reduce the overall average latency and total network power with minimum hardware cost for the fault tolerant routing algorithm for NoC.
Keywords: network on chip; NoC; fault tolerant routing; logic-based distributed routing; LBDRe; transistor reliability; simulation.
International Journal of Embedded Systems, 2013 Vol.5 No.1/2, pp.19 - 26
Received: 13 Mar 2012
Accepted: 06 Jul 2012
Published online: 15 Feb 2013 *