Title: Applying partial fault tolerance with explicit area constraints

Authors: David L. Foster; Darrin M. Hanna

Addresses: Department of Electrical and Computer Engineering, Kettering University, 1700 University Avenue Flint, MI, 48504, USA ' Department of Electrical and Computer Engineering, Oakland University, 2200 N. Squirrel Road Rochester, MI, 49309, USA

Abstract: As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Current techniques output the required circuit area based on the desired level of fault tolerance with some techniques increasing the area by over 200%. In deployed systems, however, the FPGA is fixed and the area available for adding fault tolerance is limited. As a consequence, protecting an updated, larger circuit using the same fault tolerance scheme may result in a design that no longer fits in the deployed FPGA. This situation dictates the need for a technique that can trade fault tolerance for lower area penalties. To fill this need, this paper presents a new area constrained approach which accepts available hardware resources as an input and outputs a maximally fault tolerant circuit.

Keywords: partial fault tolerance; field programmable gate arrays; FPGA; reconfigurable logic; area constrained design.

DOI: 10.1504/IJES.2013.052145

International Journal of Embedded Systems, 2013 Vol.5 No.1/2, pp.67 - 80

Received: 22 Aug 2011
Accepted: 10 Feb 2012

Published online: 15 Feb 2013 *

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