Title: Analysing ION/IOFF in ultradeep-submicron CMOS devices using grooved nMOSFETs for low-power applications
Authors: Subhra Dhar; Manisha Pattanaik; P. Rajaram
Addresses: ABV-Indian Institute of Information Technology and Management Gwalior, VLSI Lab, Department of Information Technology, Gwalior-474010, MP, India ' ABV-Indian Institute of Information Technology and Management Gwalior, VLSI Lab, Department of Information Technology, Gwalior-474010, MP, India ' Department of Physics, Jiwaji University, Gwalior-474011, MP, India
Abstract: To manage the increasing static leakage in ultra low-power applications, solutions for leakage reduction as well as improving the current drive of the device are sought at the device design and process technology levels. The influence of single corner grooves and changing concave corner angles in deep submicron and ultra deep-submicron grooved gate nMOSFET is studied to analyse the subthreshold characteristics in ultralow-power applications. ATLAS process simulator verifies that by changing the structural parameters, ON current-OFF current ratio is improved and maintained constant and be helpful for low-power applications as well as be applicable to high-speed devices.
Keywords: grooved MOSFET; concave corner angles; planar MOSFET; DIBL; deep submicron regime; negative junction depth; current drive; potential barrier; threshold voltage; ultradeep CMOS; low power applications; static leakage; leakage reduction; single corner grooves.
International Journal of Signal and Imaging Systems Engineering, 2013 Vol.6 No.1, pp.24 - 30
Received: 09 Feb 2011
Accepted: 15 Apr 2011
Published online: 20 Jan 2013 *