Title: Systolic array based motion estimation architecture of 3D DWT sub band component for video processing
Authors: Ganapathi Hegde; Pukhraj Vaya
Addresses: Department of ECE, Amrita Vishwa Vidyapeetham, Amrita School of Engineering, No. 26 & 27, Kasavanahalli, Carmelram P.O., Off. Sarjapur Road, Bangalore 560 035, Karnataka, India ' Department of ECE, Amrita Vishwa Vidyapeetham, Amrita School of Engineering, No. 26 & 27, Kasavanahalli, Carmelram P.O., Off. Sarjapur Road, Bangalore 560 035, Karnataka, India
Abstract: This paper describes Full Search Block Matching Algorithm (FSBMA) performed on 3D image in the transformed domain. An image of size N×N×8 is first transformed in to eight sub bands each of size N/2 × N/2 × 4 employing 3D Discrete Wavelet Transform (3D DWT). FSBMA performed on LLL sub band component which achieves good Peak Signal to Noise Ratio (PSNR), Compression Ratio (CR) and reduces computation complexity when compared with the original image. Modified lifting scheme based DWT and Systolic Array Architecture (SAA) based FSBMA are implemented on Field Programmable Gate Array (FPGA). 3D DWT implemented on FPGA operates at 230 MHz and consumes a power of 0.29 W, while FSBMA implemented on FPGA to reduce the computational time for motion estimation, operates at 120 MHz and consumes a power less than 0.34 W.
Keywords: 3D DWT; FSBMA; SAA; systolic array architecture; lifting scheme; systolic arrays; motion estimation; video processing; block matching algorithm; 3D images; discrete wavelet transform; image processing.
International Journal of Signal and Imaging Systems Engineering, 2012 Vol.5 No.3, pp.158 - 166
Available online: 17 Oct 2012 *Full-text access for editors Access for subscribers Purchase this article Comment on this article