Title: A simple VLSI architecture for computation of 2D DCT, quantisation and zig-zag ordering for JPEG

Authors: Vijay Kumar Sharma; Umesh C. Pati; K.K. Mahapatra

Addresses: Department of Electronics and Communications Engineering, National Institute of Technology, Rourkela, India ' Department of Electronics and Communications Engineering, National Institute of Technology, Rourkela, India ' Department of Electronics and Communications Engineering, National Institute of Technology, Rourkela, India

Abstract: In this paper, a comparative simulation study of Peak Signal to Noise Ratio (PSNR) in JPEG image compression is done using two quantisation tables, one recommended by JPEG committee and another suitable for hardware simplification. Simulation results confirm that quantisation table suitable for hardware simplification can be used for designing JPEG baseline encoder circuitry. We present a simple Finite State Machine (FSM)-based VLSI architecture from Discrete Cosine Transform (DCT) to zig-zag reordering of transformed coefficients for JPEG baseline encoder using quantisation table suitable for less complex hardware design. The proposed architecture is implemented in Xilinx FPGA as well as Synopsys DC.

Keywords: JPEG; image compression; PSNR; peak signal to noise ratio; DCT; discrete cosine transform; quantisation tables; distributed arithmetic; VLSI architecture; hardware simplification; zig-zag ordering.

DOI: 10.1504/IJSISE.2012.046743

International Journal of Signal and Imaging Systems Engineering, 2012 Vol.5 No.1, pp.58 - 65

Available online: 04 May 2012 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article