Title: Design and construction of BCH codes for enhancing data integrity in multi level flash memories

Authors: K. Rajesh Shetty; K. Ramakrishna; H. Prashantha Kumar; U. Sripati

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Karnataka, Surathkal, Srinivasanagar Post, Mangalore – 575025, India. ' Department of Electronics and Communication Engineering, National Institute of Technology Karnataka, Surathkal, Srinivasanagar Post, Mangalore – 575025, India. ' Department of Electronics and Communication Engineering, National Institute of Technology Karnataka, Surathkal, Srinivasanagar Post, Mangalore – 575025, India. ' Department of Electronics and Communication Engineering, National Institute of Technology Karnataka, Surathkal, Srinivasanagar Post, Mangalore – 575025, India

Abstract: Flash memories have found extensive application for use in storage devices. The storage capacity and reliability of these devices have increased enormously over the years. With increase in density of data storage, the raw bit error rate (RBER), associated with the storage device increases. Error control coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes for flash memories based on multi level cell (MLC) concept. This is in continuation of our work on synthesis of BCH codes for improving the performance of flash memories based on single level cells (SLC). The improvement in device integrity resulting from the use of these codes has been quantified in this paper along with computation of parameters which allows modelling of flash memory as an equivalent channel. While synthesising codes, we have adhered to the limitations imposed by the memory architecture. Use of these codes in storage devices will result in considerable enhancement of device reliability and consequently open up many new applications for this class of storage devices.

Keywords: single level cells; SLC; multilevel cells; MLC; flash memories; raw bit error rate; RBER; uncorrectable bit error rate; UBER; memory modelling; storage devices; reliability; data integrity.

DOI: 10.1504/IJICT.2012.045747

International Journal of Information and Communication Technology, 2012 Vol.4 No.1, pp.40 - 60

Published online: 27 Feb 2012 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article