Authors: Subhadip Kundu; Santanu Chattopadhyay
Addresses: Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, West Bengal, India. ' Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, West Bengal, India
Abstract: This paper addresses two methods for reducing power consumption during testing. The first one is to assign suitable values to the unspecified bits (don't cares) in the test patterns so that both static and dynamic power are reduced. The second technique discusses the issue of blocking pattern selection for reducing power consumption during circuit testing in a scan-based approach. The blocking pattern is used to prevent the scan chain transitions from reaching circuit inputs. This, though reduces dynamic power significantly, can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using genetic algorithm and use it properly so that both dynamic and leakage power are reduced.
Keywords: power consumption reduction; circuit testing; leakage current; genetic algorithms; GAs; switching activity; blocking patterns.
International Journal of Computer Aided Engineering and Technology, 2012 Vol.4 No.2, pp.101 - 125
Published online: 22 Feb 2012 *Full-text access for editors Access for subscribers Purchase this article Comment on this article