Authors: Mohamed Issad; Mohamed Anane; Nadjia Anane
Addresses: Centre de Développement des Technologies Avancées (CDTA), Cité 20 Août 1956 BP17, Baba Hassen, Alger, Algerie. ' Ecole Nationale Supérieure d'Informatique (ESI) BP 68M Oued Smar, 16309, El Harrach, Alger, Algérie. ' Centre de Développement des Technologies Avancées (CDTA), Cité 20 Août 1956 BP17, Baba Hassen, Alger, Algerie
Abstract: In this paper, the algorithm and the hardware implementation of radix-2 Montgomery modular multiplication (MMM) are presented. The operation's performances depend on the radix and the modulus size. The MMM with big modulus requires a large area for its implementation. The objective of this work is to realise an optimised intellectual property (IP) to perform this operation with a reduced area, independent of the modulus size, dedicated to low rate cryptographic applications. Our architecture uses a fixed data path size w to compute the MMM of two n-bits operands, with n >> w. To store these operands, we use embedded memory blocks (SelectRam), instead of long registers to overcome the routing complexity which is a timing consumer. The arithmetic unit (AU) is optimised at the low level (CLB), resulting in high performances AU. The proposed architecture is suitable to hybrid cryptosystem where both the symmetric and asymmetric cryptographies are used.
Keywords: Montgomery modular multiplication; high performance architectures; modular arithmetic; RSA; FPGA; intellectual property; cryptography; hybrid cryptosystems; information security; field programmable gate arrays.
International Journal of High Performance Systems Architecture, 2011 Vol.3 No.4, pp.175 - 183
Available online: 13 Feb 2012 *Full-text access for editors Access for subscribers Purchase this article Comment on this article