Article: Design and characterisation of an AES chip embedding countermeasures Journal: International Journal of Intelligent Engineering Informatics (IJIEI) 2011 Vol.1 No.3/4 pp.328 - 347 Abstract: In critical communication infrastructures, hardware accelerators are often used to speed up cryptographic calculations. Their resistance to physical attacks determines how secure the overall infrastructure is. In this paper, we describe the implementation and characterisation of an AES accelerator embedding security features against physical attacks. This AES chip is implemented in HCMOS9gp 130 nm STM technology. The countermeasure is based on duplication and works on complemented values in parallel. The chip was tested against side channel attacks showing the efficiency of the proposed countermeasure against such attacks. Fault injection tests based on the use of local laser shoots showed that the fault detection mechanism did indeed react as expected. However, using clock set-up time violations, 80% of the secret key were retrieved in less than 40 hours, thus illustrating the limits of the duplication countermeasure against a global fault attack which was published after the chip was designed. Inderscience Publishers - linking academia, business and industry through research

Title: Design and characterisation of an AES chip embedding countermeasures

Authors: Jacques Fournier; Jean-Baptiste Rigaud; Sylvain Bouquet; Bruno Robisson; Assia Tria; Jean-Max Dutertre; Michel Agoyan

Addresses: CEA-LETI Minatec, CMPGC, 880 Route de Mimet, 13541 Gardanne, France. ' Ecole Nationale Supérieure des Mines de Saint Etienne, CMPGC, 880 Route de Mimet, 13541 Gardanne, France ' CEA-LETI Minatec, CMPGC, 880 Route de Mimet, 13541 Gardanne, France. ' CEA-LETI Minatec, CMPGC, 880 Route de Mimet, 13541 Gardanne, France. ' CEA-LETI Minatec, CMPGC, 880 Route de Mimet, 13541 Gardanne, France. ' Ecole Nationale Supérieure des Mines de Saint Etienne, CMPGC, 880 Route de Mimet, 13541 Gardanne, France. ' CEA-LETI Minatec, CMPGC, 880 Route de Mimet, 13541 Gardanne, France.

Abstract: In critical communication infrastructures, hardware accelerators are often used to speed up cryptographic calculations. Their resistance to physical attacks determines how secure the overall infrastructure is. In this paper, we describe the implementation and characterisation of an AES accelerator embedding security features against physical attacks. This AES chip is implemented in HCMOS9gp 130 nm STM technology. The countermeasure is based on duplication and works on complemented values in parallel. The chip was tested against side channel attacks showing the efficiency of the proposed countermeasure against such attacks. Fault injection tests based on the use of local laser shoots showed that the fault detection mechanism did indeed react as expected. However, using clock set-up time violations, 80% of the secret key were retrieved in less than 40 hours, thus illustrating the limits of the duplication countermeasure against a global fault attack which was published after the chip was designed.

Keywords: Advanced Encryption Standard; AES; side channel attacks; circuit duplication; fault injection; fault detection; fault propagation; cryptography; security; embedded systems; chip embedding; countermeasures.

DOI: 10.1504/IJIEI.2011.044101

International Journal of Intelligent Engineering Informatics, 2011 Vol.1 No.3/4, pp.328 - 347

Received: 01 Mar 2011
Accepted: 27 Jun 2011
Published online: 28 Feb 2015 *

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Title: Design and characterisation of an AES chip embedding countermeasures

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