Title: A minimalist cache coherent MPSoC designed for FPGAs

Authors: Jorge Tortato Junior, Roberto A. Hexsel

Addresses: Datacom Telematica, Av. Carlos de Carvalho 603, Sala 122, CEP 80430-180, Curitiba, PR, Brazil. ' Departamento de Informatica, Universidade Federal do Parana (UFPR), Caixa Postal 19.081 – CEP 81531-990, Curitiba, PR, Brazil

Abstract: We describe the design and VHDL implementation of a cache coherent MPSoC named minimalist cache coherent MPSoC (MCCM). The system comprises one to eight MIPS-I processors, coherent primary data caches, memory management units, memory controller and the interconnection. We present a detailed account of the implementation, focusing on the shared memory subsystem. A simple benchmark is used to assess the overall system functionality. We compared the size of our design to that of a LEON3-based multiprocessor and found that a four-core LEON3 system needs roughly the same amount of logic/state as a six to eight cores MCCM.

Keywords: multicore; shared memory multiprocessors; cache coherence; FPGA; MPSoC; VHDL implementation; field programmable gate arrays.

DOI: 10.1504/IJHPSA.2011.040460

International Journal of High Performance Systems Architecture, 2011 Vol.3 No.2/3, pp.67 - 76

Received: 02 Jul 2010
Accepted: 29 Nov 2010
Published online: 21 Mar 2015 *

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