Title: Welded silicon for power electronic devices

Authors: Colin Parkes, S.J. Neil Mitchell, B. Mervyn Armstrong, Harold S. Gamble, Edmond T.G. Ling

Addresses: Institute of Advanced Microelectronics, Department of Electrical and Electronic Engineering, The Queen's University of Belfast, Ashby Building, Stranmillis Road, Belfast, N. Ireland, BT9 5AH, UK. ' Institute of Advanced Microelectronics, Department of Electrical and Electronic Engineering, The Queen's University of Belfast, Ashby Building, Stranmillis Road, Belfast, N. Ireland, BT9 5AH, UK. ' Institute of Advanced Microelectronics, Department of Electrical and Electronic Engineering, The Queen's University of Belfast, Ashby Building, Stranmillis Road, Belfast, N. Ireland, BT9 5AH, UK. ' Department of Elsym, University of Wales College Cardiff, Bute Building, King Edward VII Avenue, Cardiff, CFI 3YH, UK. ' Department of Elsym, University of Wales College Cardiff, Bute Building, King Edward VII Avenue, Cardiff, CFI 3YH, UK

Abstract: The improvement of many silicon power devices can be achieved by the incorporation of high resistivity layers and heavily doped buried regions into the device structure. Until recently epitaxial growth using chemical vapour deposition was the only viable method of achieving lightly doped silicon on a more heavily doped substrate. An alternative approach is the bonding of two silicon wafers. Bonding is achieved by bringing two polished silicon wafers together in a dust-free environment. The present technique employs a wash bath allowing the wafers to be bonded under liquid ensuring minimum contamination. After high temperature annealing the bonded structures can endure all standard processing treatments. Welded PN diodes yielded near-ideal characteristics and NPN bipolar transistors, with the weld interface in the P-base region, were produced with an average minority lifetime for carriers of 5ms. The viability of the process was further demonstrated by the production of large area Gate Turn-off thyristors.

Keywords: buried layers; gate turn-off; GTO thyristors; interdigitation; silicon direct bonding; SDB; silicon wafer bonding; wafer welding; wafer fabrication; power electronics; high temperature annealing.

DOI: 10.1504/IJMPT.1996.036324

International Journal of Materials and Product Technology, 1996 Vol.11 No.1/2, pp.145 - 158

Published online: 02 Nov 2010 *

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