Title: Energy efficient mapping and voltage islanding for regular NoC under design constraints

Authors: Pavel Ghosh, Arunabha Sen

Addresses: Computer Science Program, School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe, AZ 85281, USA. ' Computer Science Program, School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe, AZ 85281, USA

Abstract: Computational energy consumption of the processing elements (PEs) of a NoC can be significantly reduced by scaling down their voltage levels. This creates clusters of adjacent PEs operating at the same voltage level, known as voltage islands. Excessive number of voltage islands is undesirable from the physical design perspective and due to the overhead of level shifter energy consumption between adjacent voltage islands. Considering these issues during mapping of the PEs to the NoC routers, can potentially lead to acceptable solutions with reduced overall energy consumption. In this paper, we formulate the mapping problem as an optimisation problem. We present both optimal solution, obtained by solving a mixed integer linear program (MILP), and heuristic solution based on random greedy selection. Experimental results using benchmark and real applications show that the heuristic finds near-optimal solution in almost all cases in a very small fraction of the time required to achieve the optimal solution.

Keywords: energy efficient mapping; voltage islanding; system-on-chip; SoC; network-on-chip; NoC; mixed integer linear programming; MILP; greedy heuristics; randominisation; energy efficiency; energy consumption.

DOI: 10.1504/IJHPSA.2010.034535

International Journal of High Performance Systems Architecture, 2010 Vol.2 No.3/4, pp.132 - 144

Received: 06 Oct 2009
Accepted: 03 Mar 2010
Published online: 07 Aug 2010 *

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