Title: Architectural design of a Radix-4 CORDIC-based Radix-4 IFFT algorithm and its FPGA implementation

Authors: Kaushik Bhattacharyya, Anindya Hazra, Indranil Hatai, Swapna Banerjee

Addresses: Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, West Bengal, India. ' Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, West Bengal, India. ' Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, West Bengal, India. ' Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, West Bengal, India

Abstract: In high speed applications, it is wise to use Radix-4 algorithm, when the number of data points is the power of four, instead of using the conventional Radix-2 algorithm. In this paper a CORDIC based almost multiplier less architecture for a 16 point Radix-4 IFFT is presented. With the concurrent use of pipelining and parallelism, the advantages of minimisation of latency time and the increment of the throughput rate is achieved. The whole Radix-4 CORDIC-based Radix-4 IFFT architecture is implemented on an FPGA device with the accuracy up to 32-bit precision operating frequency at 55 MHz making it suitable for real-time applications.

Keywords: CORDIC; FPGA implementation; high bit accuracy; IFFT architecture; pipelining; parallelism; Radix-4; real time applications; field-programmable gate arrays.

DOI: 10.1504/IJSISE.2009.033761

International Journal of Signal and Imaging Systems Engineering, 2009 Vol.2 No.4, pp.201 - 215

Published online: 30 Jun 2010 *

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