Title: FPGA realisation of an area efficient SVPWM modulator for three phase induction motor drive

Authors: R.K. Pongiannan, S. Paramasivam, N. Yadaiah

Addresses: Department of Information Technology, Karpagam College of Engineering, Coimbatore – 641032, India. ' R&D Department, ESAB Engineering Services Ltd., G22, SIPCOT Industrial Park, Chennai – 602105, India. ' Department of Electrical and Electronics Engineering JNTU College of Engineering, Anantapur – 515002, India

Abstract: This paper presents an area efficient single chip field programmable gate array (FPGA) implementation for space vector pulse width modulator (SVPWM) using Q-format data representation. This new methodology in VLSI signal processing for SVPWM results in less chip resources utilisation and improved accuracy in all internal modules of the controller. The control algorithm has been developed using a very high speed integrated circuit hardware description language (VHDL) and FPGA, which provides great flexibility and technological independence. The theoretical analysis of Q-format with an example is carried out and the result shows that Q-format implementation occupies less resources and improved output accuracy of the IC compared to integer fixed point representation. The proposed Q-format representation for SVPWM is verified with simulation and experiments and the result shows the feasibility of practical implementation in real time for three phase inverter fed induction motor drive.

Keywords: field programmable gate arrays; FPGA; very high speed integrated circuit hardware description language; VHDL; area efficient SVPWM; quantity of fractional bits format; Q-format; induction motor drives; space vector pulse width modulator.

DOI: 10.1504/IJPELEC.2010.031193

International Journal of Power Electronics, 2010 Vol.2 No.2, pp.176 - 199

Published online: 25 Jan 2010 *

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