Title: Performance evaluation of MIC@R NoC for real-time applications

Authors: Rafik Ben-Tekaya, Adel Baganne, Kholdoun Torki, Rached Tourki

Addresses: EμE Lab, Faculty of Sciences Monastir, 5000, Tunisia; Lab-STICC – CNRS, UBS University, BP 92116, 56321 Lorient, France. ' Lab-STICCs – CNRS, UBS University, BP 92116, 56321 Lorient, France. ' CMP, INPG, 46 Avenue Filex Viallet 38031, Grenoble Cedex, France. ' EμE Lab, Faculty of Sciences Monastir, 5000, Tunisia

Abstract: The smart electronic homes evolution is strongly related to the System-on-Chip (SoC) development. This, in turn, requires an efficient intercommunication between its intellectual proprieties (IPs). Network-on-Chip (NoC) represents the suitable solution. This paper presents a design and implementation of MIC@R NoC architecture performed with non-uniform traffics. This architecture offers lowest routing latency (one cycle) and allows supporting several adaptive routing algorithms. The proposed NoC architecture is implemented in ASIC technology and performed in 2D mesh networks. In this paper we present a study of NoC evaluation. This NoC uses the four routing algorithms: deterministic X-Y, fully adaptive (FA), Proximity Congestion Awareness (PCA) and Proximity Hot-Spot Awareness (PHSA). The PHSA scheme is a novel routing technique proposition that is more efficient than the other ones. NoC performance evolution is measured with non-uniform traffics that are hot-spot and transpose patterns. Obtained results show that MIC@R router combined with proposed routing techniques is efficient in terms of low latency and generic aspect.

Keywords: system-on-chip; SoC; network-on-chip; NoC; real-time applications; routing algorithms; smart homes; routing latency.

DOI: 10.1504/IJCAET.2010.030549

International Journal of Computer Aided Engineering and Technology, 2010 Vol.2 No.2/3, pp.274 - 293

Available online: 21 Dec 2009 *

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