Title: A low power CMOS voltage reference circuit with sub threshold MOSFETs

Authors: S. Ramasamy, B. Venkataramani, P. Meenatchisundaram

Addresses: Dept. of ECE National Institute of Technology, Trichy – 620015, Tiruchirappalli, India. ' Dept. of ECE National Institute of Technology, Trichy – 620015, Tiruchirappalli, India. ' Dept. of ECE National Institute of Technology, Trichy – 620015, Tiruchirappalli, India

Abstract: In this paper, a novel approach is proposed for the design of low power CMOS band gap reference circuit. In the literature, an inversion technique is proposed to make the voltage reference to be independent of temperature by using parasitic bipolar transistors. In the above technique, this paper proposes the use of MOSFETs operating in sub threshold region for generating a voltage with negative temperature coefficient. The performance of the proposed scheme is studied by implementing the band gap reference circuit for 1.2 V in TSMC035 CMOS process. Studies through Mentorgraphics IC station and Eldo simulator demonstrate that the proposed scheme has a voltage reference with temperature coefficient of less than 50 ppm/°C over the temperature range of −10°C to 120°C. The proposed scheme results in 18 times lesser area and dissipates ten times lower power compared with that using parasitic bipolar transistors. The circuit technique has been validated using both NMOS and PMOS diode connected sub threshold MOSFETs for generating voltages with negative temperature coefficient.

Keywords: low power CMOS; voltage reference circuits; band gap reference; sub threshold; CTAT; PTAT; temperature coefficient; circuit design.

DOI: 10.1504/IJICT.2009.026433

International Journal of Information and Communication Technology, 2009 Vol.2 No.1/2, pp.94 - 107

Published online: 11 Jun 2009 *

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