Article: A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography Journal: International Journal of Information and Communication Technology (IJICT) 2009 Vol.2 No.1/2 pp.60 - 72 Abstract: This work presents the implementation of a tightly-coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate finite field arithmetic operations in the binary fields of F2163 and F2193, for application in a high-performance embedded system implementing elliptic curve cryptography (ECC). The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. Instead of a coprocessor, hardware acceleration of the arithmetic operation is provided by custom logic tightly coupled to the processor core and directly controlled by the instruction stream. This concept, which may be considered as a hardware-software co-design approach, is evaluated by prototyping an elliptic curve cryptosystem (ECC) on an Altera Stratix FPGA development board. Experimental results shows that for the point multiplication operation, which is the core operation in an ECC computation, the implementation with custom instructions and tightly-coupled hardware is about 50% faster than the coprocessor-based hardware. Inderscience Publishers - linking academia, business and industry through research

Title: A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography

Authors: M. Khalil-Hani, A. Irwansyah, Y.W. Hau

Addresses: VLSI-eCAD Research Laboratory (VeCAD), Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Johor, Malaysia. ' VLSI-eCAD Research Laboratory (VeCAD), Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Johor, Malaysia. ' VLSI-eCAD Research Laboratory (VeCAD), Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Johor, Malaysia

Abstract: This work presents the implementation of a tightly-coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate finite field arithmetic operations in the binary fields of F₂¹⁶³ and F₂¹⁹³, for application in a high-performance embedded system implementing elliptic curve cryptography (ECC). The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. Instead of a coprocessor, hardware acceleration of the arithmetic operation is provided by custom logic tightly coupled to the processor core and directly controlled by the instruction stream. This concept, which may be considered as a hardware-software co-design approach, is evaluated by prototyping an elliptic curve cryptosystem (ECC) on an Altera Stratix FPGA development board. Experimental results shows that for the point multiplication operation, which is the core operation in an ECC computation, the implementation with custom instructions and tightly-coupled hardware is about 50% faster than the coprocessor-based hardware.

Keywords: elliptic curve cryptography; ECC; finite field arithmetic hardware; embedded processors; custom instructions; tightly-coupled hardware; FPGA; hardware-software codesign; embedded systems; field-programmable gate arrays.

DOI: 10.1504/IJICT.2009.026430

International Journal of Information and Communication Technology, 2009 Vol.2 No.1/2, pp.60 - 72

Published online: 11 Jun 2009 *

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Title: A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography

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