Title: A hardware mechanism to reduce the energy consumption of the register file of in-order architectures
Authors: Jose L. Ayala, Marisa Lopez-Vallejo, Carlos A. Lopez-Barrio, Alexander Veidenbaum
Addresses: Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain. ' Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain. ' Department of Electronic Engineering, Universidad Politecnica de Madrid, Spain. ' Center for Embedded Computer Systems, University of California in Irvine, USA
Abstract: This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.
Keywords: register file; in-order architectures; power reduction; instruction predecode; hardware approach; energy consumption; unused registers; control logic.
International Journal of Embedded Systems, 2008 Vol.3 No.4, pp.285 - 293
Available online: 03 Jan 2009 *Full-text access for editors Access for subscribers Purchase this article Comment on this article