Title: Code compression in DSP processor systems

Authors: Piia Saastamoinen, Ilkka Saastamoinen, Jari Nurmi

Addresses: Department of Computer Systems, Tampere University of Technology, P.O. Box 553, FIN-33101, Finland. ' Department of Computer Systems, Tampere University of Technology, P.O. Box 553, FIN-33101, Finland. ' Department of Computer Systems, Tampere University of Technology, P.O. Box 553, FIN-33101, Finland

Abstract: In order to meet the demands set for time-to-market, chip size, system speed, and power, the designers are forced to continuously seek for new methods to make the optimisation and detailed refining of their designs automatically. Code compression is one possibility to go around some or even all of these design problems. With our compression methods, the memory footprint can be reduced by up to 45%, already including the area penalty created by an on-chip decompression engine. The decompression block is located between processor core and program memory. Thus the core does not need to be modified and also the performance is preserved. In addition to memory savings, memory related dynamic power consumption is reduced by 33%.

Keywords: code compression; DSP; digital signal processing; embedded systems; area minimisation; power reduction; on-chip decompression engine.

DOI: 10.1504/IJES.2008.022396

International Journal of Embedded Systems, 2008 Vol.3 No.4, pp.256 - 262

Available online: 03 Jan 2009 *

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