Title: Alternative application-specific processor architectures for fast arbitrary bit permutations

Authors: Zhijie Jerry Shi, Xiao Yang, Ruby B. Lee

Addresses: Department of Computer Science and Engineering, University of Connecticut, Storrs, CT 06269, USA. ' Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA. ' Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA

Abstract: Block ciphers are used to encrypt data and provide data confidentiality. For interoperability reasons, it is desirable to support a variety of block ciphers efficiently. Of the basic operations in block ciphers, only bit permutation is very slow on existing processors, followed by integer multiplication. Although new permutation instructions proposed recently can accelerate bit permutations in general-purpose processors, reducing the number of instructions needed to achieve an arbitrary n-bit permutation from O(n) to O(log2n), the data dependency between permutation instructions prevents them from being executed in fewer than log2n cycles, even on superscalar processors. Since Application-Specific Instruction-Set Processors (ASIPs) have fewer constraints on maintaining standard processor datapath and control conventions, six alternative ASIP approaches are proposed in this paper to achieve arbitrary 64-bit permutations in one or two cycles without increasing the cycle time. These approaches use new BFLY and IBFLY instructions. We also compare these approaches and their efficiency in performing arbitrary 64-bit permutations.

Keywords: ASIP; application specific instruction-set processors; bit permutations; block ciphers; confidentiality; cryptography acceleration; embedded systems; instruction set architecture; software encryption; symmetric-key cipher; security; interoperability.

DOI: 10.1504/IJES.2008.022393

International Journal of Embedded Systems, 2008 Vol.3 No.4, pp.219 - 228

Available online: 03 Jan 2009 *

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