Title: Power-efficient VLIW design using clustering and widening

Authors: Miquel Pericas, Eduard Ayguade, Javier Zalamea, Josep Llosa, Mateo Valero

Addresses: Computer Architecture Department, Technical University of Catalonia (UPC), Jordi Girona 1-3, Modul D6 Campus Nord, 08034 Barcelona, Spain. ' Computer Architecture Department, Technical University of Catalonia (UPC), Jordi Girona 1-3, Modul D6 Campus Nord, 08034 Barcelona, Spain. ' Computer Architecture Department, Technical University of Catalonia (UPC), Jordi Girona 1-3, Modul D6 Campus Nord, 08034 Barcelona, Spain. ' Computer Architecture Department, Technical University of Catalonia (UPC), Jordi Girona 1-3, Modul D6 Campus Nord, 08034 Barcelona, Spain. ' Computer Architecture Department, Technical University of Catalonia (UPC), Jordi Girona 1-3, Modul D6 Campus Nord, 08034 Barcelona, Spain

Abstract: Media applications exhibit large quantities of Instruction-Level Parallelism (ILP), particularly inside of loops. However, exploited ILP is limited by available resources and loop recurrences. To overcome this, current designs replicate memory ports and functional units. But as the number of units grows, the efficiency also reduces dramatically. Clustering and widening are two techniques for enabling wide issue-cores to meet technology constraints in terms of cycle time, area and power. In this paper we evaluate several VLIW designs that use these techniques. From the study we conclude that either clustering, widening or both can yield power-efficient configurations with little area requirements.

Keywords: VLIW design; numerical computations; embedded systems; wide functional units; hardware clustering; power-efficient computing, energy delay; modulo scheduling.

DOI: 10.1504/IJES.2008.020295

International Journal of Embedded Systems, 2008 Vol.3 No.3, pp.141 - 149

Available online: 14 Sep 2008 *

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