Authors: Dandan Qi, Jon C. Muzio
Addresses: Department of Computer Science, University of Victoria, Victoria, BC, Canada. ' Department of Computer Science, University of Victoria, Victoria, BC, Canada
Abstract: Various linear finite state machines have been widely used as pseudo-random test pattern generators for the built-in self-test of integrated circuits. These generators are inexpensive to use as they have the advantage of low hardware overhead. However, the Geffe generator, a classic type of non-linear finite state machine, has not been frequently studied or used in similar applications. It is known that a Geffe generator, when used as a pattern generator for digital system testing gives improved fault detection. Unfortunately, the area overhead involved is sufficiently high, thus, such a generator becomes impractical for built-in self-test. To solve such problems, we introduce two possible new designs of the Geffe generator. These new designs are based on the generator|s original architecture, so they preserve the non-linear structure. Our optimal goal is to achieve a very sharp reduction of the area overhead, and maintain a satisfactory fault detection capability. These two new designs are exercised in the fault simulations of benchmark sequential circuits. The experimental results demonstrate both of our designs can lead to fault coverage, which significantly exceeds the fault coverage of linear machines, and is comparable to the original Geffe generator.
Keywords: built-in testing; fault coverage; linear feedback shift register; nonlinear test pattern generator; design for testability; DFT; Geffe generator; nonlinear finite state machines; sequential circuits; generator design; fault detection; built-in self-test; integrated circuits; IC testing.
International Journal of Communication Networks and Distributed Systems, 2008 Vol.1 No.2, pp.179 - 194
Published online: 10 Sep 2008 *Full-text access for editors Access for subscribers Purchase this article Comment on this article