Title: A multiobjective evolutionary algorithm-based optimisation model for network on chip synthesis
Authors: Rabindra Kumar Jena, Gopal K. Sharma
Addresses: Department of IT, Institute of Management Technology, Nagpur, India. ' Department of IT, ABV-Indian Institute of Information Technology and Management, Gwalior, India
Abstract: Network on Chip (NoC) is a new paradigm for design core-based System on Chip (SoC). It is expected to provide higher computation power due to its higher clock frequencies and parallel execution of processes. This paper addresses the problem of topological mapping of Intellectual Properties (IPs) on the tile of a mesh-based NoC. As the stated problem is NPhard in nature, we propose a heuristic technique based on multiobjective Genetic Algorithm (GA) to obtain an optimal approximation of the pereto-optimal front. The evaluation performed on three randomly generated benchmarks and a real application (a M-JPEG encoder) to conform the efficiency, accuracy and scalability of the proposed approach. Our proposed approach saves up to 15–20% of energy and more than 15% of bandwidth requirement compared with the existing approaches.
Keywords: NoC optimisation; energy efficiency; performance; system level synthesis; genetic algorithms; network on chip; topological mapping; intellectual properties; evolutionary algorithms.
International Journal of Innovative Computing and Applications, 2007 Vol.1 No.2, pp.121 - 127
Published online: 22 Jan 2008 *Full-text access for editors Access for subscribers Purchase this article Comment on this article