Title: Algorithms for low power hardware synthesis from Concurrent Action Oriented Specifications (CAOS)
Authors: Gaurav Singh, Sandeep K. Shukla
Addresses: FERMAT Lab, Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA. ' FERMAT Lab, Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA
Abstract: Behavioural synthesis has received considerable attention recently and new action-oriented hardware specification formalisms have been proposed. We call such formalisms Concurrent Action Oriented Specifications (CAOS). CAOS models have low granularity concurrent atomic action descriptions with a semantics similar to Dijkstra|s guarded command language. Such models have been shown to generate efficient hardware designs, and the importance of making such CAOS-based synthesis process power-aware cannot be undervalued. In this paper, we formulate the problems of power-optimal synthesis for CAOS, discuss several heuristics and show some numerical examples illustrating the use of such heuristics during CAOS-based synthesis.
Keywords: behavioural synthesis; concurrent action-based specifications; low-power design; peak power; switching power; semantics; hardware design; power-aware computing.
International Journal of Embedded Systems, 2007 Vol.3 No.1/2, pp.83 - 92
Available online: 02 Dec 2007 *Full-text access for editors Access for subscribers Purchase this article Comment on this article