Title: Design of power-aware FPGA fabrics

Authors: Aman Gayasen, Suresh Srinivasan, N. Vijaykrishnan, Mahmut Kandemir

Addresses: Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, USA. ' Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, USA. ' Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, USA. ' Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, USA

Abstract: We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timing-critical paths run on normal Vdd, while the non-critical ones save power by using a lower Vdd. Our programmable dual-Vdd architectures and Vdd assignment algorithms provide an average power saving of 61% across the MCNC benchmarks. The second technique targets applications where configuration time is crucial. It uses Asymmetric SRAM (ASRAM) (instead of high-Vt SRAM) cells to implement the configuration memory. Our bit-inversion algorithm further reduces leakage by increasing the number of ASRAM cells that are in their preferred state.

Keywords: power consumption; FPGAs; dual-Vdd; asymmetric SRAM; ASRAM; leakage reduction; power-aware FPGA fabrics; field programmable gate arrays; power-aware computing.

DOI: 10.1504/IJES.2007.016033

International Journal of Embedded Systems, 2007 Vol.3 No.1/2, pp.52 - 64

Available online: 02 Dec 2007 *

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