Title: A new way of estimating compute-boundedness and its application to dynamic voltage scaling

Authors: Vasanth Venkatachalam, Michael Franz, Christian W. Probst

Addresses: Donald Bren School of Information and Computer Science, University of California, Irvine, CA, USA. ' Donald Bren School of Information and Computer Science, University of California, Irvine, CA, USA. ' Informatics and Mathematical Modelling, Technical University of Denmark, 2800 Kongens Lyngby, Denmark

Abstract: Many dynamic voltage scaling algorithms rely on measuring hardware events (such as cache misses) for predicting how much a workload can be slowed down with acceptable performance loss. The events measured, however, are at best indirectly related to execution time and clock frequency. By relating these two indicators logically, we propose a new way of predicting a workload|s compute-boundedness that is based on direct observation, and only requires measuring the total execution cycles for the two highest clock frequencies. Our predictor can be used to develop dynamic voltage scaling algorithms that are more system-aware than current approaches.

Keywords: dynamic voltage scaling; DVS; performance estimation; virtual machines.

DOI: 10.1504/IJES.2007.016030

International Journal of Embedded Systems, 2007 Vol.3 No.1/2, pp.17 - 30

Available online: 02 Dec 2007 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article