Article: Power control in semiconductor chips: integration of reinforcement learning and dynamic modelling Journal: International Journal of Information and Communication Technology (IJICT) 2025 Vol.26 No.46 pp.76 - 94 Abstract: As semiconductor technology enters the nanoscale era, power control has become a major challenge impeding chip performance. Traditional heuristic methods fail to handle complex dynamic workloads, while pure reinforcement learning lacks stability and safety. This paper proposes a hybrid intelligent control framework integrating reinforcement learning with dynamic physical modelling. Offline-trained power and performance models offer prior guidance and safety constraints for online decisions. Experiments using Google production cluster data show the framework achieves an average power of 101.3 W - 21.3% lower than on-demand strategies - and a tail latency of 34.1 ms with only 1.2% violation rate. The energy efficiency reaches 15.6 instructions per joule, outperforming existing methods. This study provides an effective solution for energy-aware chip-level power management and introduces new ideas for intelligent cyber-physical systems. Inderscience Publishers - linking academia, business and industry through research

Title: Power control in semiconductor chips: integration of reinforcement learning and dynamic modelling

Authors: Zhanhan Hu

Addresses: School of Computer Science, North China Institute of Aerospace Engineering, Langfang, 065000, China

Abstract: As semiconductor technology enters the nanoscale era, power control has become a major challenge impeding chip performance. Traditional heuristic methods fail to handle complex dynamic workloads, while pure reinforcement learning lacks stability and safety. This paper proposes a hybrid intelligent control framework integrating reinforcement learning with dynamic physical modelling. Offline-trained power and performance models offer prior guidance and safety constraints for online decisions. Experiments using Google production cluster data show the framework achieves an average power of 101.3 W - 21.3% lower than on-demand strategies - and a tail latency of 34.1 ms with only 1.2% violation rate. The energy efficiency reaches 15.6 instructions per joule, outperforming existing methods. This study provides an effective solution for energy-aware chip-level power management and introduces new ideas for intelligent cyber-physical systems.

Keywords: power consumption control; reinforcement learning; dynamic modelling; energy efficiency optimisation; chip management.

DOI: 10.1504/IJICT.2025.150604

International Journal of Information and Communication Technology, 2025 Vol.26 No.46, pp.76 - 94

Received: 30 Aug 2025
Accepted: 26 Sep 2025
Published online: 17 Dec 2025 *

Title: Power control in semiconductor chips: integration of reinforcement learning and dynamic modelling

Keep up-to-date