Title: VLSI realisation of an efficient image scalar using Vedic mathematics

Authors: Ramadevi Vemula; K. Manjunatha Chari

Addresses: Gitam University, Rudraram, Hyderabad, Telangana 502329, India ' Gitam University, Rudraram, Hyderabad, Telangana 502329, India

Abstract: A low-complexity algorithm using Vedic mathematics is intended for VLSI realisation of an efficient image scalar. The proposed scalar comprises of a modified area pixel interpolator, edge detector and Vedic multiplier. To decrease the obscuring and aliasing effects created by the area-pixel model and to conserve the image edge features productively an edge catching method is embraced. Moreover, a Vedic division unit is utilised for enhancing execution of the scaling processor without any rounding error correction techniques. It additionally accomplishes advancement at all levels of digital systems reducing power consumption. The proposed architecture is capable to achieve 5.28-K gates count using 200 MHZ, and computation time is 14.37 ns synthesised by 0.13-μm CMOS technology. Through comparison with previous techniques, this work can reduce gate counts by 18% and want only a one-line-buffer memory.

Keywords: image scalar; line buffer; sharpening filter; Vedic mathematics; VLSI.

DOI: 10.1504/IJAIP.2025.147658

International Journal of Advanced Intelligence Paradigms, 2025 Vol.30 No.3, pp.187 - 202

Received: 24 Apr 2018
Accepted: 07 Dec 2018
Published online: 25 Jul 2025 *

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